Smc-networks SMC91C95 Manuale Utente

SMC91C95PRELIMINARYISA/PCMCIA Full Duplex Single-ChipEthernet and Modem Controller with RAMFEATURES• ISA/PCMCIA Single Chip Ethernet ControllerWith Mo

10DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION81 nByte HighEnablenSBHE I with pullup ISA - Byte High Enable input. Asserted (low)b

100BOARD SETUP INFORMATIONISA MODEThe following parameters are obtained from theEEPROM as board setup information:ETHERNET INDIVIDUAL ADDRESSI/O BASE

101REGISTER are written in the EEPROMlocations defined by the IOS2-0 pins.The three least significant bits of the CONTROLREGISTER (EEPROM SELECT, RELO

102For example, if an odd pointer value is loaded,first a byte is pre-fetched into the FIFO, andimmediately a full word is pre-fetchedcompleting three

103FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODECONFIGURATION REG.BASE REG.CONFIGURATION REG.BASE REG.CONFIGURATION REG.BASE REG.CONFIGURATION RE

104OPERATIONAL DESCRIPTIONMAXIMUM GUARANTEED RATINGS*Operating Temperature Range...

105PARAMETER SYMBOLMIN TYP MAX UNITS COMMENTSInput Leakage(All I and IS buffers exceptpins withpullups/pulldowns)Low Input LeakageHigh Input LeakageII

106PARAMETER SYMBOLMIN TYP MAX UNITS COMMENTSOD16 Type BufferLow Output LevelOutput LeakageVOLIOL-100.5+10VµAIOL = 16 mAVIN = 0 to VCCOD162 Type Buffe

107PARAMETER MIN TYP MAX UNITS10BASE-TReceiver Threshold Voltage 100 mVReceiver Squelch 300 400 585 mVReceiver Common Mode Range 0 VDDTransmitter Outp

108TIMING DIAGRAMSFIGURE 18 - PCMCIA MEMORY READ TIMINGA[5:0], nREGnCE1nOED[15:0]DATA VALIDt1t2t3t4t5t60 min30 max5 maxParameter Min Typ Max Unitst1 A

109FIGURE 19 - PCMCIA MEMORY WRITE TIMINGA[5:0], nREGnCE1nWED[15:0 (Din)]250 mint4t1t50 mint2Parameter Min Typ Max Unitst1 nWE Pulse Width 150 nst2 Ad

11DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTIONnInterruptRequestnIREQ PCMCIA - Active low interrupt request output.Pin acts as a Re

110A[15:0]nREGnIOIS16t4nINPACKnCEnIORDD[15::0]t1t5t7t6nMCSt18t15t3t10t17t2t16t9t11t8t12t13t14t36t19t20FIGURE 20 - I/O READ TIMING(Table on the followi

111Parameter Min Typ Max Unitst1 Address setup before nIORD low 70 nst2 nCEI, nCE2 setup before nIORD low 5 nst3 nREG setup before nIORD low 5 nst4 nI

112A[15:0]nREGnIOIS16t24nCE1nCE2nIOWRD[15::0]t25t27t26nMCSt30t23t32t22t31t21t28t29t34t35t33t36FIGURE 21 - (I/O WRITE TIMING)(Table on the following pa

113Parameter Min Typ Max Unitst21 Address setup before nIOWR low 70 nst22 nCE1, nCE2 setup before nIOWR low 5 nst23 nREG setup before nIOWR low 5 nst2

114FIGURE 22 - CARD CONFIGURATION REGISTERS - READ/WRITE PCMCIA MODE (A15=1)nsnsnsnsnsnsnsnsns405030925152515600t57t58t59t60t61t62t63t64t65Write Data

115FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLESnsnsnsnsnsnsnsnsns354005518501525150Parametert46t47t48t20t49t50t51t52t53nIORD Delay tonREG Low to Control

116FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES550152515185309t51t52t47t49t48t50t20t54t55validvalidA0-9,A15nREGnCE1,nCE2nIOWRD0-15t47t48t49t50t51t52t20

117FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0)nsns2025nWE to nFWE DelayAddress, nREG, nCE1 Delay to nFCSt66t67Parametermintypmaxunitst67t67

118FIGURE 26 - RINGOUT FOR L39/C39 ROCKWELL MODEMS ENTERING/EXITINGPOWERDOWNnMPWDN]MRINGOUTBParameter Min Typ Max Unitst1 MRINGOUTB Pulse Entering Pow

119FIGURE 27 - ISA CONSECUTIVE READ CYCLESBALE Tied HighVALID ADDRESSVALID ADDRESSVALID DATAOUTVALID DATAOUTt15t4t3t20t5t6ZZA0-15AEN, nSBHEnIOCS16nIOR

12DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTIONnIOIS16 PCMCIA - Active low output assertedwhenever the SMC91C95 is in 16 bit mode,a

120FIGURE 28 - ISA CONSECUTIVE WRITE CYCLESVALID ADDRESSVALID ADDRESSt15t4t3t20A0-15AEN, nSBHEnIOCS16nIOWRD0-15VALID DATA INVALID DATAt7t8BALE Tied Hi

121FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLESt20A0-15AEN,nSBHEnIOCS16nIOWRD0-D15VALID ADDRESSVALID ADDRESSnIORDt9t10ZZZVALID DATAVALID DATAIOCH

122FIGURE 30 - DATA REGISTER SPECIAL READ ACCESSA0-15(ISA)AEN,nSBHEnIOCS16D0-D15nIORDVALID DATAVALID ADDRESSIOCHRDYOUTt9t18t19ZZParametermintypmaxunit

123FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESSnIOCS16D0-D15VALID ADDRESSA0-15(ISA)AEN,nSBHEnIOWRVALID DATA INIOCHRDYt18ZZParametermintypmaxunits154

124FIGURE 32 - 8-BIT MODE REGISTER CYCLESFIGURE 33 - EXTERNAL ROM READ ACCESSA0-15(ISA)AENnIORDD0-7nIOWRt3t3t5ZVALID DATA OUTZVALID DATA INt7t8VALID A

125FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALEAENnIOCS16A0-15,nSBHEnIORDBALEnIOWRt4VALIDt1t2t15t3t1t2t3t4t15Address, nSBHE Setup to BALE FallingAd

126FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALEAddress Setup to BALE FallingAddress Hold after BALE FallingAddress Setup to Control ActivenMEMRD Lo

127FIGURE 36 - EEPROM READEEDIEESKEEDOEECSEESK Falling to EEDO, EECS Changingt21Parametermintypmaxunits100nst21t2109346 is typically the serial EEPROM

128FIGURE 37 - EEPROM WRITEEESKEEDOEEDIEECSEESK Falling to EEDO, EECS Changingt21Parametermintypmaxunits100nst21t219346 is typically the serial EEPROM

129FIGURE 38 - MEMORY READ TIMINGFIGURE 39 - MEMORY WRITE TIMINGADDRESSPOINTERREGISTERDATAREGISTERnIOWRnIORDIOCHRDY/nWAIT (Z)t44t44 Pointer Register R

13DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION26 MIDLEN1 O4 Powerdown output to modem controller. Thispin is active (high) when ei

130FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMITFIGURE 41 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BYFALLING RXCLK)nTXENTXDTX

131FIGURE 42 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND AUI)TPETXPTPETXNTPETXDNTPETXDPTXPTXNt31t32t33t34TPETXP to TPETXN SkewTPETXP(N) to TPETX

132FIGURE 43 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T)1101010100first bit decodedt35t361101010100t37first bit decodedt38RECPRECNnCRS(intern

133FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T)ba1/0last bitTPERXPTPERXNRECPRECNnCRS(internal)t39t39Receiver Turn Off DelayParametermi

134FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T)ba1/0last bitTPETXPTPETXNTXPTXNt40t41Transmit Output High to Idle in Half-Step ModeTra

135FIGURE 46 - COLLISION TIMING (AUI)t42t43COLLPCOLLNCOL(internal)t42t43Collision Turn On DelayCollision Turn Off DelayParametermintypmaxunits50350nsn

1360Hd DHeEeb0.08(0.003) MA2 A1YcL1L0.25GAGE PLANESYMBOLMILLIMETERINCHMIN. NOM. MAX. MIN. NOM. MAX. 0.05 0.95 0.13 0.0913.9013.9015.9015.90 0.45 0

300 Kennedy DriveHauppauge, NY 11788(516) 435-6000FAX (516) 231-6004Circuit diagrams utilizing SMC products are included as a means of illustrating t

14DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION16 n16 BitModemnMIS16 I with pullup Input. When low, it indicates a 16 bit modem,oth

15DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION10 nReceiveLEDnRXLED OD16 Internal ENDEC - Receive LED output.ReceiveClockRXCLK I wi

16DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION125126AUI Collision COLPCOLNDiff. Input AUI collision differential inputs. A collisi

17DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION116 nExternalENDECnXENDEC I with pullup When tied low the SMC91C95 is configuredfor

18Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROMTPETXPTPETXNTPETXDPTPETXDNTPERXPTPERXNTXPTXNRECPRECNCOLPCOLNXTAL1XTAL2EEDIEECSEED

19Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA CardMODEM CHIPSETSMC91C95nCE1 nCE2 nREG nWEnIREQD0-D15RESETnIORD nIOWRA0-A9, A15nI

2TABLE OF CONTENTSFEATURES...

20Figure 3 - SMC91C95 Internal Block DiagramMODEMINTERFACETWISTED PAIRTRANSCEIVERDATABUSADDRESSBUSCONTROLBUSINTERFACEARBITERCSMA/CDENDECAUIMMU10BASE-T

21FUNCTIONAL DESCRIPTIONThe SMC91C95 consists of an integrated Ethernetcontroller mapped entirely in I/O space, as well assupport for an external Mode

22Table 2 - Bus Transactions in PCMCIA ModeA0 nCE1 nCE2 D0-D7 D8-D158 BIT MODE ((IOis8=1) + (nEN16=1).(16BIT=0)) 0 0 X even byte -1 0 X odd byte -X 1

23Table 3 - SMC91C95 Address SpacesSIGNALSUSEDISA PCMCIAON-CHIP DEPTH WIDTHPCMCIAAttributeMemorynOE nWE N Y N(externalROM)Up to 32klocations, onlyeven

24The internal DMA interface can arbitrate for RAMaccess and request memory from the MMU whennecessary.An encoder/decoder block interfaces theCSMA/CD

25FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREAPAGE = 256 bytesPHYSICAL MEMORYTX PACKET NUMBERRX PACKET NUMBERMMUMMU2K TX AREA2K RX AREA11-BIT

26FIGURE 5 - TRANSMIT QUEUES AND MAPPINGBABCSTATUSCOUNTDATASTATUSCOUNTDATAPACKET #APACKET #BPACKET NUMBERREGISTERTX FIFOTOCSMALINEAR ADDRESS MMU MAPPI

27FIGURE 6 - RECEIVE QUEUE AND MAPPINGDEDESTATUSCOUNTDATASTATUSCOUNTDATAPACKET #DPACKET #EFIFO PORTSREGISTERRX FIFOFROMCSMALINEAR ADDRESS MMU MAPPINGM

28FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATHBUS INTERFACEARBITERMMUBUFFER RAMCSMA/CDENDECTWISTED PAIRTRANSCEIVERAUI10BASETDATA BUSADDRE

29PACKET FORMAT IN BUFFER MEMORYThe packet format in memory is similar for theTRANSMIT and RECEIVE areas. The firstword is reserved for the status wo

3Network Interface• Integrates 10BASE-T TransceiverFunctions:- Driver and Receiver- Link Integrity Test- Receive Polarity Detection andCorrection• Int

30BYTE COUNT - Divided by two, it defines thetotal number of words including the STATUSWORD, the BYTE COUNT WORD, the DATAAREA and the CONTROL BYTE.Th

31RECEIVE FRAME STATUS WORD This word is written at the beginning of each receive frame in memory. It is not available as a register.HIGHBYTEALGNERRBR

32INTERRUPT STRUCTUREThe SMC91C95 merges two main interruptsources into a single interrupt line. One source isthe Ethernet interrupt and the other is

33RESET LOGICThe pins and bits involved in the different resetmechanisms are:RESET - Input PinPOR - Internal circuit activated by PowerOnnMRESET - O

34POWERDOWN LOGICThe pins and bits involved in powerdown are:1. PWRDWN/TXCLK - Input pin valid whenXENDEC is not zero (0).2. Pwrdwn bits in ECSR and M

35Table 6 - Powerdown FunctionsPOWERDOWNENTEREDPOWERDOWNEXITEDPOWERSDOWN:DOES NOTPOWER DOWN(B2) Power StatenWAKEUP (Pin)When pin is lowand reset isina

36Internal VS External Attribute Memory MapThe Internal VS External EPROM attributememory decodes are shown below. This allowsthe designer to not requ

37I/O SPACE(ISA and PCMCIA Mode)In ISA mode, the base I/O space is determined bythe IOS0-IOS2 inputs and the EEPROM contents.A4-A15 are compared again

38Table 9 - Internal I/O Space MappingBANK0 BANK1 BANK2 BANK3 BANK4 BANK50 TCR CONFIG MMUCOMMANDMT0-MT1 ECOR(low byte) ECSR (high byte)MCOR(low byte)M

39BANK SELECT REGISTEROFFSET NAME TYPE SYMBOLE BANK SELECTREGISTERREAD/WRITE BSRHIGHBYTE0 0 1 1 0 0 1 10 0 1 1 0 0 1 1LOWBYTEBS2 BS1 BS0X X X X X 0 0

4GENERAL DESCRIPTIONThe SMC91C95 is a VLSI Ethernet Controllerthat combines ISA and PCMCIA interfaces, aswell as an interface to a companion modemchip

40I/O SPACE - BANK0OFFSET NAME TYPE SYMBOL0 TRANSMIT CONTROLREGISTERREAD/WRITE TCRThis register holds bits programmed by the CPU to control some of th

41LOOP - Local Loopback. When set, transmitframes are internally looped to the receiver afterthe encoder/decoder. Collision and Carrier Senseare ignor

42I/O SPACE - BANK0OFFSET NAME TYPE SYMBOL2 EPH STATUS REGISTER READ ONLY EPHSRThis register stores the status of the last transmitted frame. This re

43detection for magic packet - enabled bynWAKEUPEN pin (92 QFP) or WAKEUP_EN inCTR.NOTE: If the MP mode is activated using thenWAKEUPEN pin, the pin m

44I/O SPACE - BANK0OFFSET NAME TYPE SYMBOL4 RECEIVE CONTROLREGISTERREAD/WRITE RCRHIGHBYTESOFT_RSTFILT_CAR0 0 0 0STRIP_CRCRXEN0 0 0 0 0 0 0 0LOWBYTEALM

45I/O SPACE - BANK0OFFSET NAME TYPE SYMBOL6 COUNTER REGISTER READ ONLY ECRCounts four parameters for MAC statistics. When any counter reaches 15 an in

46I/O SPACE - BANK0OFFSET NAME TYPE SYMBOL8 MEMORY INFORMATIONREGISTERREAD ONLY MIRHIGHBYTEFREE MEMORY AVAILABLE (IN BYTES * 256 * M)0 0 0 1 1 0 0 0LO

47I/O SPACE - BANK0OFFSET NAME TYPE SYMBOLA MEMORY CONFIGURATIONREGISTERLower Byte -READ/WRITEUpper Byte -READ ONLYMCRHIGHBYTEMEMORY SIZE MULTIPLIER0

48I/O SPACE - BANK1OFFSET NAME TYPE SYMBOL0 CONFIGURATION REGISTER READ/WRITE CRThe Configuration Register holds bits that define the device configura

49INT SEL1 INT SEL0 INTERRUPT PINUSED00110101INTR0INTR1INTR2INTR3

5receive are fully independent. It has 6 kbytes ofinternal memory and the MMU managesmemory in 256 byte pages. The memory sizeaccommodates the incre

50I/O SPACE - BANK1OFFSET NAME TYPE SYMBOL2 BASE ADDRESS REGISTER READ/WRITE BARFor ISA mode only, this register holds the I/O address decode option c

51I/O SPACE - BANK1OFFSET NAME TYPE SYMBOL4 THROUGH 9 INDIVIDUAL ADDRESSREGISTERSREAD/WRITE IARThese registers are loaded starting at wordlocation 20h

52I/O SPACE - BANK1OFFSET NAME TYPE SYMBOLA GENERAL PURPOSE REGISTER READ/WRITE GPRHIGHBYTEHIGH DATA BYTE0 0 0 0 0 0 0 0LOWBYTELOW DATA BYTE0 0 0 0 0

53I/O SPACE - BANK1OFFSET NAME TYPE SYMBOLC CONTROL REGISTER READ/WRITE CTRHIGHBYTE0RCV_BADPWRDWN WAKEUP_ENAUTORELEASE10 0 0 0 0 X X 1LOWBYTELEENABLEC

54CR ENABLE - Counter Roll over Enable. Whenset it enables the CTR_ROL bit as one of theinterrupts merged into the EPH INT bit. Defaultslow (disabled)

55Table 10 - PCMCIA EEPROM to SRAM Memory MapATTRIBUTE MEMORYHOST ADDRESS (HEX)ATTRIBUTEDATAEEPROM ADDRESSIN WORDSSMC91C95 SRAMIN BYTES000 Data byte 0

56I/O SPACE - BANK2OFFSET NAME TYPE SYMBOL0 MMU COMMAND REGISTER WRITE ONLYBUSY Bit ReadableMMUCRThis register is used by the CPU to control the memor

57110 6) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting apacket just loaded into RAM. The packet number to be enqueued

58I/O SPACE - BANK2OFFSET NAME TYPE SYMBOL2 PACKET NUMBER REGISTER READ/WRITE PNRPACKET NUMBER AT TX AREA0 0 0 0 0 0 0 0PACKET NUMBER AT TX AREA - The

59I/O SPACE - BANK2OFFSET NAME TYPE SYMBOL4 FIFO PORTS REGISTER READ ONLY FIFOThis register provides access to the read ports of the Receive FIFO and

6Fast block move operation for load/unload:CPU sees packet bytes as if storedcontiguouslyHandles 16 bit transfers regardless ofaddress alignmentAccess

60I/O SPACE - BANK2OFFSET NAME TYPE SYMBOL6 POINTER REGISTER READ/WRITE PTRHIGHBYTERCVAUTOINCR.READ ETEN 0 POINTER HIGH0 0 0 0 0 0 0 0LOWBYTEPOINTER L

61I/O SPACE - BANK2OFFSET NAME TYPE SYMBOL8 THROUGH Ah DATA REGISTER READ/WRITE DATADATA HIGHDATA LOWDATA REGISTER - Used to read or write the databuf

62I/O SPACE - BANK2OFFSET NAME TYPE SYMBOLC INTERRUPT STATUS REGISTER READ ONLY ISTERCVINTEPH INTRX_OVRN INTALLOCINTTXEMPTYINTTX INT RCV INTX 0 0 0 0

63WAKE_UP - “Magic Packet” is received ifenabledRX_OVRN INT - Set when the receiver overrunsdue to a failed memory allocation. The RX_OVRNbit of the E

64FIGURE 9 - INTERRUPT STRUCTURE543210543210INTERRUPTSTATUSREGISTERINTERRUPTMASKREGISTEROEnOEnRDIST16DATABUSD0-7D8-15EDGE DETECTORON LINK ERRLEMASKCTR

65I/O SPACE - BANK 3OFFSET NAME TYPE SYMBOL0 THROUGH 7 MULTICAST TABLE READ/WRITE MTLOWBYTEMULTICAST TABLE 00 0 0 0 0 0 0 0HIGHBYTEMULTICAST TABLE 10

66I/O SPACE - BANK3OFFSET NAME TYPE SYMBOL8 MANAGEMENT INTERFACE READ/WRITE MGMTHIGHBYTEnXNDECIOS2 IOS1 IOS00 0 1 1LOWBYTEMDOE MCLK MDI MDO0 0 1 1 0 0

67I/O SPACE - BANK3OFFSET NAME TYPE SYMBOLA REVISION REGISTER READ ONLY REVHIGHBYTE0 0 1 1 0 0 1 1LOWBYTECHIP REV0 1 0 0 0 0 0 0CHIP - Chip ID. Can be

68I/O SPACE - BANK 3OFFSET NAME TYPE SYMBOLC EARLY RCV REGISTER READ/WRITE ERCVHIGHBYTE0 0 1 1 0 0 1 1LOWBYTERCVDISCRDERCV THRESHOLD0 0 0 1 1 1 1 1RCV

69THEORY OF OPERATIONPC Card 5.0 treats the individual functions of amultifunction PCMCIA applicationindependently. Card and Socket Services(C&SS

7PIN REQUIREMENTSFUNCTION ISA PCMCIA NUMBER OFPINSSYSTEM ADDRESS BUS A0-A15A16A17A18A19AENA0-A15nFWEnFCSnCE1nREG21SYSTEM DATA BUS D0-D15 D0-D15 16SYST

702. FDSE (Full Duplex Switched Ethernet).Enabled by FDSE bit in TCR bit. When theSMC91C95 is configured for FDSE, itstransmit and receive paths will

71TYPICAL FLOW OF EVENTS FOR TRANSMITS/W DRIVER CSMA/CD SIDE1 ISSUE ALLOCATE MEMORY FOR TX - NBYTES - the MMU attempts to allocate Nbytes of RAM.2 WA

72TYPICAL FLOW OF EVENTS FOR RECEIVES/W DRIVER CSMA/CD SIDE1 ENABLE RECEPTION - By setting the RXENbit.2 A packet is received with matching address.Me

73FIGURE 10 - ETHERNET INTERRUPT SERVICE ROUTINEISRSave Bank Select & Address Ptr RegistersMask 91C94 InterruptsRead Interrupt RegisterCall TX IN

74FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMUTX FIFOTX COMPLETIONFIFORX FIFOCSMA/CDLOGICALADDRESSPACKET #MMUPHYSICAL ADDRESSRAMCPU ADD

75FIGURE 12 - RX INTRRX INTRWrite Ad. Ptr. Reg. & Read Word 0 from RAMDestination Multicast?Read Words 2, 3, 4 from RAM for Address FilteringAddre

76FIGURE 13 - TX INTR(Assumes Auto Release Option Selected)Write Into Packet Number RegisterTX Status OK?TX INTRSave Pkt Number RegisterRead TXDONE Pk

77FIGURE 14 - TXEMPTY INTRTXEMPTY INTRWrite Acknowledge Reg. with TXEMPTY Bit SetRead TXEMPTY & TX INTRAcknowledge TXINTRRe-Enable TXENAReturn to

78FIGURE 15 - DRIVER SEND AND ALLOCATE ROUTINESALLOCATEIssue "Allocate Memory" Command to MMURead Interrupt Status RegisterEnqueue PacketSet

79MEMORY PARTITIONINGUnlike other controllers, the SMC91C95 doesnot require a fixed memory partitioningbetween transmit and receive resources. TheMMU

8FUNCTION ISA PCMCIA NUMBER OFPINSCRYSTAL OSC. XTAL1XTAL2XTAL1XTAL22POWER VDDAVDDVDDAVDD12GROUND GNDAGNDGNDAGND1210BASE-T INTERFACE TPERXPTPERXNTPETXP

80TX INT bit - Set whenever the TX completionFIFO is not empty.TX EMPTY INT bit - Set whenever the TXFIFO is empty.AUTO RELEASE - When set, successful

81Table 11 - Attribute Memory Decodes Using Serial EPROMATTRIBUTEMEMORYADDRESSEXTERNAL EPROMSTOREINTERNAL SRAMSTORE (512 BYTES)CONFIGURATIONREGISTERS0

82PCMCIA CONFIGURATION REGISTERS DESCRIPTIONEthernet Function (Base Address 8000h)8000h - Ethernet Configuration Option Register (ECOR)7 6 5 4 3 2 1 0

838002h - Ethernet Configuration and Status Register (ECSR)7 6 5 4 3 2 1 0IOIs8 Pwrdwn Intr IntrACK0 0 0 0 0 0 0 0BIT 7 - Not definedBIT 6 - Not defin

84I/O Base Register 0 & 1 (I/O Base 0 & 1) Address 800Ah & 800Ch800Ah - Ethernet I/O BASE Register 07 6 5 4 3 2 1 0A7 A6 A5 A4 0 0 0 00 0

85Modem Function (Base Address 8020h)8020h - Modem Configuration Option Register (MCOR)7 6 5 4 3 2 1 0SRESET LevIREQ EnableIREQEnableBase andLimitEnab

868022h - Modem Configuration and Status Register (MCSR) Address 8022h7 6 5 4 3 2 1 0Changed SigChg IOIs8 Reserved Audio Pwrdwn Intr IntrACK0 0 0 0 0

878024h - Pin Replacement Register (PRR)7 6 5 4 3 2 1 0Cready/-BsyRready/-Bsy0 0 0 0 0 0 1 0Cready/-Bsy: This bit is set to a one when thebit Rready/

888028h - Extended Status Register(ESR)7 6 5 4 3 2 1 0RINGEVENT RINGENABLE0 0 0 0 0 0 0 0RINGEVENT: This bit is latched to a one at thestart of each

89802Ah - Modem I/O BASE Register 07 6 5 4 3 2 1 0A7 A6 A5 A4 A3 0 0 00 0 0 0 0 0 0 0802Ch - Modem I/O BASE Register 17 6 5 4 3 2 1 0A15 A14 A13 A12 A

9DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL TYPE DESCRIPTION113 nROM/nPCMCIAI/O4 withpullupThis pin is sampled at the end of RESET.When this pin

908032h - Modem I/O Size RegisterModem I/O Size Mask0 0 0 0 0 1 1 1The I/O Size Register holds a bit mask used tospecify the number of address lines d

91FUNCTIONAL DESCRIPTION OF THE BLOCKSMEMORY MANAGEMENT UNITThe MMU interfaces the on-chip RAM on oneside and the arbiter on the other for addressand

92The arbiter uses the pointer register as the CPUprovided address, and the internal DMAaddress from the CSMA/CD side as theaddresses to be provided t

93write cycle starts and there is more than twobytes in the write FIFO.The cycle time is defined as the time betweenleading edges of read from the Dat

94Packets with bad CRC can be received ifthe RCV_BAD bit in the configurationregister is set.5) If AUTO_RELEASE is set, a release isissued by the DMA

95FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERSTX FIFOCOMPLETIONFIFORX FIFOCSMA/CDLOGICALADDRESSPACKET #MMUPHYSICAL ADDRESSRAMCPU ADDRESSC

96CSMA BLOCKThe CSMA/CD block is first interfaced via itscontrol registers in order to define itsoperational configuration. From then on, theDMA inte

97Only when 16 retries are reached, theCSMA/CD block will clear the TXENA bit, andCPU intervention is required. The DMA will notautomatically restart

98can be divided into transmit and receivefunctions.Transmit FunctionsManchester EncodingThe PHY encodes the transmit data receivedfrom the MAC. The

99Reverse Polarity FunctionIn the 10BASE-T mode, the PHY monitors forreceiver polarity reversal due to crossed wiresand corrects by reversing the sign